 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| MOTOROLA Order Number: MC100EP195/D Rev. 0.1, 05/1999 Semiconductor Components MC100EP195 PROGRAMMABLE DELAY CHIP Product Preview * * * * * * * * * * * * * 32 Lead TQFP PLASTIC PACKAGE CASE TBD Programmable Delay Chip 10ns Maximum Case Delay Range 20ps/Delay Step Resolution >1.0GHz Bandwidth PECL mode: 3.0V to 5.5V VCC with VEE = 0V ECL mode: 0V VCC with VEE = -3.0V to -5.5V On Chip Cascade Circuitry 75K Input Pulldown Resistors Q Output will default LOW with inputs open or at VEE ESD Protection: >4KV HBM, >200V MM VBB Output New Differential Input Common Mode Range Moisture Sensitivity Level 1, Indefinite Time Out of Drypack Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 * Transistor Count = TBD devices Pinout: 32-Lead (TBD) The MC100EP195 is a programmable delay chip (PDC) designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential LVECL input transition. The delay section consists of a chain of gates organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the EP195 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:8], which are latched on chip by a high signal on the latch enable (LEN) control. When LEN is low latch inputs are transparent and will allow dynamic changes. Because the delay programmability of the EP195 is achieved by purely differential ECL gate delays the device will operate at frequencies of >1.0 GHz while maintaining over 600 mV of output swing. This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. (c) Motorola, Inc. 1999 1 ECLinPS PlusTM MC100EP195 The EP195 thus offers very fine resolution, at very high frequencies, that is selectable entirely from a digital input allowing for very accurate system clock timing. A tenth latched input, D9, is provided for cascading multiple PDC's for increased programmable range. The cascade logic allows full control of multiple PDC's, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating. PIN NAMES Pin IN/IN EN D[0:9] Q/Q LEN SET MIN SET MAX CASCADE VBB Function Signal Input Input Enable Mux Select Inputs Signal Output Latch Enable Min Delay Set Max Delay Set Cascade Signal Output Output Voltage Reference LOGIC DIAGRAM - SIMPLIFIED VBB IN IN EN * 1.25 * 1.5 0 LEN SET MIN SET MAX LEN 7BITLATCH LATCH D Q 1 1 Q Q CASCADE 1 1 0 1 0 1 1 0 1 1 1 0 1 4 GATES 0 1 8 GATES 0 1 16 GATES 0 1 32 GATES 0 1 64 GATES 0 1 CASCADE CASCADE D0 D1 D2 * DELAYS ARE 25% OR 50% LONGER THAN * STANDARD (STANDARD 80 PS) D3 D4 D5 D6 D7 D8 D9 2 Home Page - http://scgtomorrow.motorola.com MC100EP195 ECLinPS PlusTM DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) Symbol IIH IEE Characteristic Input HIGH Current Power Supply Current Min 0C Typ Max 150 TBD Min 25C Typ Max 150 Min 85C Typ Max 150 TBD Unit A mA Condition AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND) 0C Symbol tPLH tPHL Characteristic Propagation Delay IN to Q; Tap = 0 IN to Q; Tap = 508 EN to Q; Tap = 0 D7 to CASCADE Programmable Range tPD (max) - tPD (min) Step Delay D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High Linearity Duty Cycle Skew tPHL-tPLH Setup Time D to LEN D to IN EN to IN Hold Time LEN to D IN to EN Release Time EN to IN SET MAX to LEN SET MIN to LEN Jitter Output Rise/Fall Time 20-80% (Q) 20-80% (CASCADE) <5.0 TBD <5.0 <5.0 D1 D0 30 0 D1 D0 30 0 D1 D0 30 0 2 3 ps 4 ps 5 ps 1 ps Min Typ Max Min 25C Typ Max Min 85C Typ Max Unit ps Notes TBD ps ps 20 40 80 120 240 480 960 1920 3840 7 6 tRANGE t Lin tSKEW ts th tR tjit ps ps 8 tr tf 1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 3. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than 75 mV to that IN/IN transition. 4. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than 75 mV to that IN/IN transition. 5. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing binary counts on the control inputs Dn). Typically the device will be monotonic to the D0 input, however under worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB the device is guaranteed to be monotonic over all specified environmental conditions and process variation. 8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques. Home Page - http://scgtomorrow.motorola.com 3 ECLinPS PlusTM MC100EP195 ADDRESS BUS (A0-A8) A9 D2 D3 D4 D5 D6 D7 D8 D9 D2 D3 D4 D5 D6 D7 D8 D9 Q CASCADE CASCADE SET MAX Q VCCO OUTPUT SET MIN BIT 7 Q6 D7 LEN Reset Reset Q7 D1 D0 LEN VEE IN INPUT CASCADE CASCADE SET MAX IN SET MIN VBB EN D1 EP195 Chip #1 D0 VCC VCCO Q Q VCCO LEN VEE IN IN VBB EP195 Chip #2 VCC VCCO Figure 1. Cascading Interconnect Architecture Chip #1 on the other hand will have both SET MIN and SET MAX de-asserted so that its delay will be controlled entirely by the address bus A0-A8. If the delay needed is greater than can be achieved with 127.75 gate delays (1111111 on the A0-A8 address bus) D9 will be asserted to signal the need to cascade the delay to the next EP195 device. When D9 is asserted the SET MIN pin of chip #2 will be de-asserted and the delay will be controlled by the A0-A8 address bus. Chip #1 on the other hand will have its SET MAX pin asserted resulting in the device delay to be independent of the A0-A8 address bus. When the SET MAX pin of chip #1 is asserted the D0 and D1 latches will be reset while the rest of the latches will be set. In addition, to maintain monotonicity an additional gate delay is selected in the cascade circuitry. As a result when D9 of chip #1 is asserted the delay increases from 127.75 gates to 128 gates. A 128 gate delay is the maximum delay setting for the EP195. To expand this cascading scheme to more devices one simply needs to connect the D9 input and CASCADE outputs of the current most significant EP195 to the new most significant EP195 in the same manner as pictured in Figure 1. The only addition to the logic is the increase of one line to the address bus for cascade control of the second PDC. Cascading Multiple EP195's To increase the programmable range of the EP195 internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP195's without the need for any external gating. Furthermore this capability requires only one more address line per added EP195. Obviously cascading multiple PDC's will result in a larger programmable range however this increase is at the expense of a longer minimum delay. Figure 1 illustrates the interconnect scheme for cascading two EP195's. As can be seen, this scheme can easily be expanded for larger EP195 chains. The D9 input of the EP195 is the cascade control pin. With the interconnect scheme of Figure 1 when D9 is asserted it signals the need for a larger programmable range than is achievable with a single device. An expansion of the latch section of the block diagram is pictured below. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D9 of chip #1 above is low the cascade output will also be low while the cascade bar output will be a logical high. In this condition the SET MIN pin of chip #2 will be asserted and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Since the RESET and SET inputs of the latches are overriding any changes on the A0-A8 address bus will not affect the operation of chip #2. TO SELECT MULTIPLEXERS BIT 0 D0 LEN Reset Reset Q0 BIT 1 D1 LEN Reset Reset Q1 D2 BIT 2 Q2 BIT 3 D3 LEN Reset Reset Q3 D4 BIT 4 Q4 D5 BIT 5 Q5 EN BIT 6 D6 LEN Reset Reset CASCADE CASCADE LEN Reset Reset LEN Reset Reset LEN Reset Reset SET MIN SET MAX Figure 2. Expansion of the Latch Section of the E195 Block Diagram 4 Home Page - http://scgtomorrow.motorola.com MC100EP195 ECLinPS PlusTM OUTLINE DIMENSIONS TBD SUFFIX PLASTIC PACKAGE CASE TBD Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 Customer Focus Center: 1-800-521-6274 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 1-602-244-6609 ASIA / PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, Motorola Fax Back System - US & Canada ONLY 1-800-774-1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. - http://sps.motorola.com/mfax/ 852-26629298 HOME PAGE: http://motorola.com/sps/ JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan. 81-3-5487-8488 Home Page - http://scgtomorrow.motorola.com MC100EP195/D 5 |
Price & Availability of MC100EP195D
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |